library ieee;
use ieee.std_logic_1164.all;

entity shiftRegSelectLogic is
	port (
		clk, clr, load, hold : in bit;
		z1, z2 : out bit
	);
end entity shiftRegSelectLogic;

architecture DATAFLOW of shiftRegSelectLogic is
    
    signal orOut : bit_vector(1 downto 0);
    signal andOut : bit;
    
    begin
		orOut(0) <= hold or clr;
		orOut(1) <= andOut or clr;
		andOut <= load and (not hold);
		
		z2 <= orOut(1);
		z1 <= orOut(0);
    
end architecture DATAFLOW;

architecture STRUCTURAL of shiftRegSelectLogic is
	
	component and2
	
	port(a,b : in bit;
		z : out bit
	);
	
	end component;
	
	component notDataFlow
	
	port(a : in bit;
		z : out bit
		);
	end component;
	
	component or2
	
	port(a,b : in bit;
		z : out bit
	);
	
	end component;
	
	for all : and2 use entity work.and2(DATAFLOW); 
	for all : notDataFlow use entity work.notDataFlow(DATAFLOW);
	for all : or2 use entity work.or2(DATAFLOW);
	
	signal or1Z : bit;
	signal or2Z : bit;
	signal holdNot : bit;
	signal loadNot : bit;
	
begin

	or1Z <= hold or clr;
	or2Z <= load or clr;
	Z1 <= or1Z and (not load);
	Z2 <= or2Z and (not hold);

end architecture STRUCTURAL;
